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mbm29lv002tc -70/-90 / mbm29lv002bc -70/-90 mbm29lv002tc -70/-90 /mbm29lv002bc -70/- 90 cover sheet data sheet (retired product) this product has been retired and is not recommended for new designs . availability of this document is retained for reference and historical purposes only. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansi on product. any changes that have been made are the result of normal data sheet improvem ent and are noted in the document revision summary. for more information please contact your local sales office for additional information about spansion memory solutions. publication number mbm29lv002tc/bc revision ds05-20863-5e issue date july 26, 2007
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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and ch anges will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20863-5e fujitsu semiconductor data sheet retired product y ds05-20863-5e_july 26, 2007 flash memory cmos 2m (256k 8) bit mbm29lv002tc - 70/-90 /mbm29lv002bc -70/-90 general description the mbm29lv002tc/bc are a 2m-bit, 3.0 v-only flash me mory organized as 256k bytes of 8 bits each. the mbm29lv002tc/bc are offered in a 40-pin tsop(1) and 40-pin son packages. these devices are designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. the standard mbm29lv002tc/bc offer access times 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. (continued) product line up pac k ag e s part no. mbm29lv002tc/mbm29lv002bc ordering part no. v cc = 3.3 v +0.3 v ?0.3 v -70 ? v cc = 3.0 v +0.6 v ?0.3 v ?-90 max address access time (ns) 70 90 max ce access time (ns) 70 90 max oe access time (ns) 30 35 40-pin plastic tsop (1) 40-pin plastic tsop (1) (fpt-40p-m06) (fpt-40p-m07) marking side marking side
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 5 (continued) the mbm29lv002tc/bc are pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the eras e and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29lv002tc/bc are programmed by executing th e program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase comm and sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, th e devices automatically time the erase pulse widths and verify proper cell margin. any individual sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29lv002tc/bc are erased when shipped from the factory. the devices feature single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. fujitsu?s flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm2 9lv002tc/bc memories electric ally erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 6 features ? single 3.0 v read, program, and erase minimizes system level power requirements compatible with jedec-standard commands uses same software commands as e 2 proms compatible with jedec-standard world-wide pinouts 40-pin tsop(1) (package suffix: ptn ? normal bend type, ptr ? reversed bend type) minimum 100,000 program/erase cycles high performance 70 ns maximum access time sector erase architecture one 16k byte, two 8k bytes, one 32k byte, and three 64k bytes any combination of sectors can be concurrently erased. also supports full chip erase boot code sector architecture t = top sector b = bottom sector embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector embedded program tm * algorithms automatically writes and verifies data at specified address data polling and toggle bit feature for detection of program or erase cycle completion ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode low v cc write inhibit 2.5 v erase suspend/resume suspends the erase operation to allow a read data in another sector within the same device sector protection hardware method disables any combination of sectors from program or erase operations sector protection set function by extended sector protection command temporary sector unprotection temporary sector unpro tection via the reset pin * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 7 pin assignments a 16 a 15 a 14 a 13 a 12 a 11 a 9 a 8 we reset n.c. ry/by a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 mbm29lv002tc/mbm29lv002bc normal bend tsop (1) a 17 v ss n.c. a 19 a 10 dq 7 dq 6 dq 5 dq 4 v cc v cc n.c. dq 3 dq 2 dq 1 dq 0 oe v ss ce a 0 (marking side) (fpt-40p-m06) a 1 a 2 a 3 a 4 a 5 a 6 a 7 ry/by n.c. reset we a 8 a 9 a 11 a 12 a 13 a 14 a 15 a 16 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 mbm29lv002tc/mbm29lv002bc reverse bend a 0 ce v ss oe dq 0 dq 1 dq 2 dq 3 n.c. v cc v cc dq 4 dq 5 dq 6 dq 7 a 10 a 19 n.c. v ss a 17 (marking side) (fpt-40p-m07) n.c. n.c.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 8 pin description pin name function a 17 to a 0 address inputs dq 7 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector unprotection n.c. no internal connection v ss device ground v cc device power supply
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 9 block diagram logic symbol v ss v cc we ce a 17 to a 0 oe erase voltage generator dq 7 to dq 0 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb timer for program/erase reset ry/by buffer ry/by 18 a 17 to a 0 we oe ce dq 7 to dq 0 8 reset ry/by
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 10 device bus operation legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see ? dc characteristics? for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see ?sector address tables (mbm29lv002tc)? in flexible sector-erase architecture. *2 : refer to ?sector protection? in functional description. *3 : we can be v il if oe is v il , oe at v ih initiates the write operations. *4 : v cc = 3.3 v 10% *5 : it is also used for the extended sector protection. mbm29lv002tc/002bc user bus operations operation ce oe we a 0 a 1 a 6 a 9 a 10 dq 7 to dq 0 reset auto-select manufacturer code * 1 llhlllv id lcodeh auto-select device code * 1 llhhllv id lcodeh read * 3 llha 0 a 1 a 6 a 9 a 10 d out h standby h x x x x x x x high-z h output disable l h h x x x x x high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 a 10 d in h enable sector protection * 2, * 4 lv id lhlv id xxh verify sector protection * 2, * 4 llhlhlv id lcodeh temporary sector unprotection * 5 xxxxxxx x x v id reset (hardware)/standby x x x x x x x x high-z l
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 11 notes : ? address bits x = ?h? or ?l? for all address commands except or program address (pa) and sector address (sa) ? bus operations are defined in ?mbm29lv002tc/002bc user bus operations? in device bus operation. ? ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 17 , a 16 , a 15 , a 14 , and a 13 will uniquely select any sector. ? rd =data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. ? both read/reset commands are functionally equivalent, resetting the device to the read mode. ? command combinations not described in ?mbm29lv002tc/bc standard command definitions table? are illegal. mbm29lv002tc/002bc standard command definitions command sequence bus write cycles req?d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h ? ? ? ? ? ? ? ? ? ? read/reset 3 555h aah 2aah 55h 555h f0h ra rd ? ? ? ? autoselect 3 555h aah 2aah 55h 555h 90h ? ? ? ? ? ? program 4 555h aah 2aah 55h 555h a0h pa pd ? ? ? ? chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend erase can be suspended during sector erase with addr. (?h? or ?l?). data (b0h) sector erase resume erase can be resumed after suspend with addr. (?h? or ?l?). data (30h)
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 12 spa: sector address to be protected. set sector address (sa) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0). sd: sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1 : this command is valid while fast mode. *2 : this command is valid while reset = v id . *3 : the data ?00h? is also acceptable. * : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. mbm29lv002tc/002bc extended command definitions command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read cycle addr data addr data addr data addr data set to fast mode 3 555h aah 2aah 55h 555h 20h ? ? fast program * 1 2 xxxh a0h pa pd ? ? ? ? reset from fast mode * 1 2 xxxh 90h xxxh f0h* 3 ???? extended sector protect * 2 4 xxxh 60h spa 60h spa 40h spa sd mbm29lv002tc/002bc sector protection verify autoselect codes type a 17 to a 13 a 10 a 6 a 1 a 0 code (hex) manufacture?s code x v il v il v il v il 04h device code mbm29lv002tc x v il v il v il v ih 40h mbm29lv002bc x v il v il v il v ih c2h sector protection sector addresses v il v il v ih v il 01h* expanded autoselect code table type code dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacture?s code 04h 00000100 device code mbm29lv002tc40h 01000000 mbm29lv002bcc2h 11000010 sector protection 01h 00000001
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 13 flexible sector-erase architecture one 16k byte, two 8k bytes, one 32k byte, and three 64k bytes individual-sector, multiple-sec tor, or bulk-erase capability individual or multiple-sector protection is user definable. sector address tables (mbm29lv002tc) sector address a 17 a 16 a 15 a 14 a 13 address range sa0 0 0 x x x 00000h to 0ffffh sa1 0 1 x x x 10000h to 1ffffh sa2 1 0 x x x 20000h to 2ffffh sa3 1 1 0 x x 30000h to 37fffh sa4 1 1 1 0 0 38000h to 39fffh sa5111013a000h to 3bfffh sa6 1 1 1 1 x 3c000h to 3ffffh sector address tables (mbm29lv002bc) sector address a 17 a 16 a 15 a 14 a 13 address range sa0 0 0 0 0 x 00000h to 03fffh sa1 0 0 0 1 0 04000h to 05fffh sa2 0 0 0 1 1 06000h to 07fffh sa3 0 0 1 x x 08000h to 0ffffh sa4 0 1 x x x 10000h to 1ffffh sa5 1 0 x x x 20000h to 2ffffh sa6 1 1 x x x 30000h to 3ffffh mbm29lv002tc sector architecture mbm29lv002bc sector architecture 16k byte 8k byte 8k byte 32k byte 64k byte 64k byte 64k byte 3ffffh 3bfffh 39fffh 37fffh 2ffffh 1ffffh 0ffffh 00000h 3ffffh 2ffffh 1ffffh 0ffffh 07fffh 05fffh 03fffh 00000h 64k byte 64k byte 64k byte 32k byte 8k byte 8k byte 16k byte
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 14 functional description read mode the mbm29lv002tc/bc have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the de lay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or change ce pin from ?h? or ?l? standby mode there are two ways to implement the standby mode on the mbm29lv002tc/bc devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 a. the device can be read with standard access time (t ce ) from either of these standby modes. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = ?h?. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = ?h? or ?l?). under this condition the current is consumed is less than 5 a. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29lv002tc/bc data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, mbm29lv002tc/bc automatica lly switch themselves to low power mode when mbm29lv002tc/bc addresses remain stably during access fine of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 a (cmos level). since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and mbm29lv002tc/bc read-out the data for changed addresses. output disable with the oe input at a logic high level (v ih ), output from the devi ces are disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the readin g out of a binary code from the devi ces and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are don?t cares except a 0 , a 1 , a 6 , and a 10 . (see ?mbm29lv002tc/002bc sector protection verify autoselect codes? in device bus operation.)
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 15 the manufacturer and device codes may also be read via the command register, for instances when the mbm29lv002tc/bc are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in ?mbm29lv 002tc/002bc standard co mmand definitions? in device bus operation. (refer to ?autoselect command?.) byte 0 (a 0 = v il ) represents the manufacturer?s code (fujitsu = 04h) and (a 0 = v ih ) represents the device identifier code (mbm29lv002tc = 40h and mbm29lv002bc = c2h). these two bytes/words are given in ?mbm29lv002tc/002bc sector protection verify autoselect codes? and ?expanded autoselect code table? in device bus operation. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see ?mbm29lv002tc/002bc sector protection verify autoselect codes? and ?expanded autoselect code ta b l e ? i n device bus operation.) write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29lv002tc/bc feature hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 6). the sector protection feature is enabled using programming equipment at the user?s site. the devices are shipped with all sectors unprotected. alternatively, fujitsu may program and protect sectors in the factory prior to shiping the device. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il , and a 6 = v il . the sector addresses (a 17 , a 16 , a 15 , a 14 , and a 13 ) should be set to the sector to be protected. ?sector address tables (mbm29lv002tc)? and ?sector address tables (mbm29lv002bc)? in flexible sector-erase architecture define the sector address for each of the seven (7) individual sectors. programming of th e protection circuitry begin s on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see ? (10) ac waveforms for sector protection timing diagram? in timing diagram and ? (5) sector protection algorithm? in flow chart and for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 17 , a 16 , a 15 , a 14 , and a 13 ) while (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) will produce a logi cal ?1? code at device output dq 0 for a protected sector. otherwise the devices will read 00h for un protected sector. in this mode, the lower order addresses, except for a 0 , a 1 , a 6 , and a 10 are don?t cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 17 , a 16 , a 15 , a 14 , and a 13 ) are the desired sector address will produce a logical ?1? at dq 0 for a protected sector. see ?mbm29lv002tc/ 002bc sector protection verify autoselect codes? and ?expanded autoselect code table? in device bus operation for autoselect codes.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 16 temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29lv002tc/bc devices in order to change data. the se ctor unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously prot ected sectors will be protected again. see ? (11) temporary sector unprotection timing diagram? in timing diagram and ? (6) temporary sector unprotection algorithm? in flow chart. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data valu es or writing them in the improper sequence will re set the devices to the read mode. ?mbm29lv002tc/002bc standard command definitions? in device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. th e devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard micr oprocessor read cycles will retrieve array data. this default va lue ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible wh ile the devices reside in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves t he manufacture code of 04h. a read cycle from address xx01h returns the device code (mbm29lv002tc = 40h and mbm29lv002bc = c2h). (see ?mbm29lv002tc/002bc sector protection verify autoselect codes? and ?expanded autoselect code table? in device bus operation.) all manufacturer an d device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address xx02h. scanning the sector addresses (a 17 , a 16 , a 15 , a 14 , and a 13 ) while (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) will produce a logical ?1? at device output dq 0 for a protected sector. the programming verification should be perform margin mode on the protected sector. (see ?mbm29lv002tc/002bc user bus operation?, ?mbm29lv002tc/002bc sector protection verify autoselect codes? and ?expanded autoselect code table? in device bus operation.) to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 17 byte programming the devices are programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two ?unlock? write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see ?hardware sequence flags? in functional description.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip du ring this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data ?0? cannot be programmed back to a ?1?. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm bu t a read from read /reset mode will show that the data is still ?0?. only erase operations can convert ?0?s to ?1?s. ?embedded program tm algorithm? in flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates when the data on dq 7 is ?1? (see ?write operation status?.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) ?embedded erase tm algorithm? in flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is la tched on the falling edge of write pulse, while the command (data=30h) is latched on the rising edge of write pulse. after time-out of 50 s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writ ing the six bus cycle operation s on ?mbm29lv002tc/002bc standard command definitions? in device bus operation. this sequenc e is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s ot herwise that command will not be acce pted and erasure will start. it is
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 18 recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 s from the rising edge of the last write pulse will initia te the execution of the sector erase comm and(s). if another fa lling edge of the write pulse occurs within the 50 s time-out window the time r is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see ?dq 3 sector erase timer?.) any command other than sector erase or erase suspend during this time-o ut period will reset the devices to the r ead mode, ignoring the previous command string. resetting the devices once ex ecution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to ?write operation status? for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (6 to 0). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprog ram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 s time out from the rising edge of the write pulse for the last sector erase command pulse and terminates when the data on dq 7 is ?1? (see ?write operation status?.) at which time the devices return to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase ?embedded erase tm algorithm? in flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes t he time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are don?t cares when writing the erase suspend or erase resume command. when the erase suspend command is writ ten during the se ctor erase operation, the device will take a maximum of 20 s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic ?1?, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see ?dq 2 togle bit ii?.) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the eras e-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or by the toggle bit i
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 19 (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend comman d can be written after the chip has resumed erasing. extended command (1) fast mode mbm29lv002tc/bc has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for prog ramming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is nece ssary to write fast mode re set command into the command register. (refer to ?embedded program tm algorithm for fast mode? in flow chart.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to ?embedded program tm algorithm for fast mode? in flow chart.) (3) extended sector protection in addition to normal sector protection, the mbm29l v002tc/bc has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector addresses pins (a 17 , a 16 , a 15 , a 14 , and a 13 ) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 150 s. to verify programming of the protection circuitry, the sector addresses pins (a 17 , a 16 , a 15 , a 14 , and a 13 ) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) should be set and write a command (40h). following the command write, a logical ?1? at device output dq 0 will produce for protected sector in the read operation. if the ou tput data is logical ?0 ?, please repeat to write extended sector protect command (60h ) again. to terminate the operatio n, it is necessary to set reset pin to v ih .
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 20 write operation status *1 : performing successive read oper ations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic ?1? at the dq 2 bit. however, successive reads from th e erase-suspended sector will cause dq 2 to toggle. notes: ? dq 0 and dq 1 are reserve pins for future use. ? dq 4 is fujitsu internal use only. dq 7 data polling the mbm29lv002tc/bc devices feature data polling as a method to indicate to the host th at the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device w ill produce the true data last written to dq 7 . during the embedded erase algorithm, an atte mpt to read the device will produce a ?0? at the dq 7 output. upon completion of the embedded erase algorithm an attempt to re ad the device will produ ce a ?1? at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in ?data polling algorithm? in flow chart. for chip erase and sector erase, the data polling is valid after th e rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29lv002tc/bc data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that byte?s valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is only active during the embedd ed programming algorithm, embedded erase algorithm or sector erase time-out. (see ?hardware sequence flags? in functional description.) see ? (6) ac waveforms for data polling during embedded al gorithm oper ations? in timing diagram for the data polling timing specifications and diagrams. hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle* 1 00 1* 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 21 dq 6 toggle bit i the mbm29lv002tc/bc also feature the ?toggle bit i? as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid da ta will be read on the next successive atte mpts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having chan ged. in erase, the devices will erase a ll the selected sectors except for the ones that are protected. if all selected sectors are pr otected, the chip will toggle the toggle bi t for about 100 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see ? (6) ac waveforms for toggle bit i during embedded algorithm operations? in timing diagram for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or er ase time has exceeded th e specified limits (inter nal pulse count). under these conditions dq 5 will produce a ?1?. this is a failure conditi on which indicates that the program or erase cycle was not successfully completed. data polling dq 7 , dq 6 is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditio ns (to appr oximately 2 ma). the oe and we pins will control the output disable functi ons as described in ?mbm29lv002tc/002bc user bus operations? in device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a ?1.? please note th at this is not a device failure condit ion since the device s were incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector er ase timer window is still open. if dq 3 is high (?1?) the internally controlled erase cycle has begun; attempts to write subsequen t commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (?0?), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. refer to ?hardware sequence flags? in functional description.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 22 dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-r ead mode, successive reads from th e erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indica te a logic ?1? at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also ?hardware sequence flags? in functional description and ? (12) dq 2 vs.dq 6 ? in timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. *1 : performing successive read oper ations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic ?1? at the dq 2 bit. however, successive reads from t he erase-suspended se ctor will cause dq 2 to toggle. ry/by ready/busy the mbm29lv002tc/bc provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/ write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands with the exception of the erase suspend command. if the mbm29lv002tc/bc are placed in an erase suspend mode, the ry/by output will be high, by means of connecting with a pull-up resister to v cc . during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to ? (8) ry/by timing diagram during program/erase operations? and ? (9) reset /ry/by timing diagram? in timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase-suspend read (erase-suspended sector) * 1 1 1 toggle erase-suspend program dq 7 toggle * 1 1 * 2
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 23 reset hardware reset the mbm29lv002tc/bc devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 s after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tr i-stated. if a hardware reset occurs during a program or eras e operation, the data at th at particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see ? (9) reset /ry/by timing diagram? in timing diagram for the timing diagram. refer to ?temporary sector unprotection? for additional functionality. if hardware reset occurs during embe dded erase algorithm, th ere is a possibility that the erasing sector(s) cannot be used. data protection the mbm29lv002tc/bc are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after su ccessful completion of spec ific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition t he device will reset to the read mode. su bsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure th at the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if embedded erase algorithm is in terrupted, there is possi bility that the erasing sector(s) cannot be used. write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of write pulse. the internal state machine is automatically reset to the read mode on power-up.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 24 absolute maximum ratings *1 : minimum dc voltage on input or i/o pins are ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins are v cc +0.5 v. during voltage transitions, outputs may overshoot to v cc +2.0 v for periods of up to 20 ns. *2 : minimum dc input voltage on a 9 , oe and reset pins are ?0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe and reset pins are +13.0 v which may overshoot to 14.0 v for periods of up to 20 ns. voltage difference between input voltage and supply voltage (v in ? v cc ) do not exceed 9 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions note : operating ranges define those limits between which the functionality of the devices are guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg ? 55 + 125 c ambient temperature with power applied t a ? 40 + 85 c voltage with respect to ground all pins except a 9 , oe and reset * 1 v in , v out ? 0.5 v cc + 0.5 v power supply voltage * 1 v cc ? 0.5 + 5.5 v a 9 , oe , acc, and reset * 2 v in ? 0.5 + 13.0 v parameter symbol value unit min max ambient temperature t a ? 40 + 85 c power supply voltage mbm29lv002tc/bc-70 v cc + 3.0 + 3.6 v mbm29lv002tc/bc-90 v cc + 2.7 + 3.6 v
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 25 maximum overshoot/ maximum undershoot +0.6 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns maximum undershoot waveform v cc +0.5 v +2.0 v v cc +2.0 v 20 ns 20 ns 20 ns maximum overshoot waveform 1 +13.0 v v cc +0.5 v +14.0 v 20 ns 20 ns 20 ns note: this waveform is applied for a 9 , oe, and reset. maximum overshoot waveform 2
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 26 dc characteristics *1 : the i cc current listed includes both the dc operating current and the frequency dependent component. *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : applicable to sector protection function. *5 : (v id ? v cc ) do not exceed 9 v. parameter symbol test conditions min max unit input leakage current i li v in = v ss to v cc , v cc = v cc max ?1.0 +1.0 a output leakage current i lo v out = v ss to v cc , v cc = v cc max ?1.0 +1.0 a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v ?35 a v cc active current * 1 i cc1 ce = v il , oe = v ih , f=10 mhz ? 22 ma ce = v il , oe = v ih , f=5 mhz ? 12 ma v cc active current * 2 i cc2 ce = v il , oe = v ih ?35ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v ?5 a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ss 0.3 v ?5 a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v ?5a input low level v il ??0.50.6v input high level v ih ?2.0v cc + 0.3 v voltage for autoselect, sector protection,and temporary sector unprotection (a 9 , oe , reset ) * 4, * 5 v id ?11.512.5v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min ? 0.45 v output high voltage level v oh1 i oh = ?2.0 ma, v cc = v cc min 2.4 ? v v oh2 i oh = ?100 a. v cc ? 0.4 ? v low v cc lock-out voltage v lko ?2.32.5v
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 27 ac characteristics read only operations note : test conditions: output load: 1 ttl gate and 30 pf (mbm29lv002tc/bc-70) 1 ttl gate and 100 pf (mbm29lv002tc/bc-90) input rise and fall times: 5 ns input pulse levels: 0.0 v or 3.0 v timing measurement reference level input: 1.5 v output:1.5 v parameter symbol test setup -70 -90 unit jedec standard min max min max read cycle time t avav t rc ?70?90?ns address to output delay t avqv t acc ce = v il oe = v il ? 70 ? 90 ns chip enable to output delay t elqv t ce oe = v il ? 70 ? 90 ns output enable to output delay t glqv t oe ??30?35ns chip enable to output high-z t ehqz t df ??25?30ns output enable to output high-z t ghqz t df ??25?30ns output hold time from addresses, ce or oe , whichever occurs first t axqx t oh ?0?0?ns reset pin low to read mode ? t ready ??20?20 s c l 3.3 v diodes = in3064 or equivalent 2.7 k ? device under test in3064 or equivalent 6.2 k ? notes: c l = 30 pf including jig capacitance (mbm29lv002tc/bc-70) c l = 100 pf including jig capacitance (mbm29lv002tc/bc-90) test conditions
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 28 write/erase/program operations *1 : this does not include the preprogramming time. *2 : this timing is for sector protection operation. parameter symbol mbm29lv002tc/bc unit -70 -90 jedec standard min typ max min typ max write cycle time t avav t wc 70 ?? 90 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address hold time t wlax t ah 45 ?? 45 ?? ns data setup time t dvwh t ds 35 ?? 45 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns output enable setup time ? t oes 0 ?? 0 ?? ns output enable hold time read ?t oeh 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 45 ?? ns ce pulse width t eleh t cp 35 ?? 45 ?? ns write pulse width high t whwl t wph 25 ?? 25 ?? ns ce pulse width high t ehel t cph 25 ?? 25 ?? ns byte programming operation t whwh1 t whwh1 ? 8 ?? 8 ? s sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ? s v cc setup time ? t vcs 50 ?? 50 ?? s rise time to v id * 2 ?t vidr 500 ?? 500 ?? ns voltage transition time * 2 ?t vlht 4 ?? 4 ?? s write pulse width * 2 ?t wpp 100 ?? 100 ?? s oe setup time to we active * 2 ?t oesp 4 ?? 4 ?? s ce setup time to we active * 2 ?t csp 4 ?? 4 ?? s recover time from ry/by ?t rb 0 ?? 0 ?? ns reset pulse width ? t rp 500 ?? 500 ?? ns reset hold time before read ? t rh 200 ?? 200 ?? ns program/erase valid to ry/by delay ? t busy ?? 90 ?? 90 ns delay time from embedded output enable ?t eoe ?? 30 ?? 35 ns
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 29 erase and programmin g performance pin capacitance note : test conditions t a = + 25c, f = 1.0 mhz parameter limits unit comments min typ max sector erase time ? 1 10 s excludes programming time prior to erasure byte programming time ? 8 300 s excludes system-level overhead chip programming time ? 2.1 6.2 s excludes system-level overhead erase/program cycle 100,000 ? ? cycle ? parameter symbol test setup typ max unit input capacitance c in v in = 0 7 8 pf output capacitance c out v out = 0 8 10 pf control pin capacitance c in2 v in = 0 9 11 pf
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 30 timing diagram key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h ?h? or ?l? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?off? state we oe ce t acc t df t ce t oe outputs t rc address address stable high-z output valid high-z t oeh (1) ac waveforms for read operations
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 31 reset t acc t oh outputs t rc address address stable high-z output valid t rh (2) ac waveforms for hardware reset/read operations
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 32 t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out (3) ac waveforms for alternate we controlled program operations notes : ? pa is address of the memory location to be programmed. ? pd is data to be programmed at byte address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates last two bus cycles out of four bus cycle sequence.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 33 t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h dout ce 555h pa pa data pollong 3rd bus cycle t ws t wh t ghel pd (4) ac waveforms for alternate ce controlled program operations notes : ? pa is address of the memory location to be programmed. ? pd is data to be programmed at byte address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates last two bus cycles out of four bus cycle sequence.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 34 v cc ce oe address data t wp we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h 30h for sector erase (5) ac waveforms chip/sector erase operations *: sa is the sector address for sector erase. addresses = 555h for chip erase.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 35 t oeh t oe t whwh1 or 2 ce oe t eoe we data t df t ch t ce high-z high-z dq 7 = valid data dq 6 to dq 0 valid data dq 7 * dq 7 dq 6 to dq 0 data dq 6 to dq 0 = output flag (6) ac waveforms for data polling during embedded algorithm operations *: dq 7 = valid data (the device has completed the embedded operation.) t oeh ce we oe dq 6 data dq 6 = toggle dq 6 = toggle dq 6 = stop toggling valid * t oe t oes (7) ac waveforms for toggle bit i during embedded algorithm operations *: dq 6 stops toggling. (the device has completed the embedded operation.)
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 36 rising edge of the last we signal ce ry/by we t busy entire programming or erase operations (8) ry/by timing diagram during program/erase operations t rp reset t ready ry/by we t rb (9) reset /ry/by timing diagram
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 37 t vlht sax a 17 , a 16 , a 15 , a 14 , a 13 say a 0 a 6 a 9 12 v 3 v t vlht oe 12 v 3 v t vlht t vlht t oesp t wpp t csp we ce t oe 01h data vcc a 1 t vcs (10) ac waveforms for sector protection timing diagram sax : sector address for initial sector say : sector address for next sector
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 38 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period (11) temporary sector unprotection timing diagram dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe (12) dq 2 vs. dq 6 note : dq 2 is read from the erase-suspended sector.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 39 (13) extended sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected time-out : time-o ut window = 150 s (min) spay reset a 6, a 10 oe we ce data a 1 v cc a 0 address spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 40 flow chart no yes program command sequence (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address last address ? program address/program data start programming completed (1) embedded program tm algorithm embedded algorithms
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 41 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequence (see below) data polling or toggle bit successfully completed chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h erasure completed start (2) embedded erase tm algorithm embedded algorithms
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 42 dq 7 = data? no no dq 7 = data? dq 5 = 1? yes yes no read (dq 7 to dq 0 ) addr. = va read (dq 7 to dq 0 ) addr. = va yes start fail pass (3) data polling algorithm note : dq 7 is rechecked even if dq 5 = ?1? because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 43 dq 6 = toggle? dq 5 = 1? read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" read dq 7 to dq 0 addr. = "h" or "l" start no no no yes yes yes *1 *1, *2 program/erase operation not complete.write reset command program/erase operation complete dq 6 = toggle? read dq 7 to dq 0 addr. = "h" or "l" *1, *2 (4) toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to ?1?.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 44 setup sector addr. (a 17 , a 16 , a 15 , a 14 , a 13 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id a 6 = ce = v il , reset = v ih a 0 = v il , a 1 =v ih plscnt = 1 time out 100 s read from sector (addr. = sa, a 0 = v il , a 1 = v ih , a 6 =v il ) increment plscnt no yes protect another sector? data = 01h? plscnt = 25? device failed start sector protection command remove v id from a 9 write reset command remove v id from a 9 write reset command (5) sector protection algorithm
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 45 reset = v id * 1 perform erase or program operations reset = v ih start temporary sector unprotection completed* 2 (6) temporary sector unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again.
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 46 (7) extended sector protection algorithm to sector protection yes no no plscnt = 1 no yes protection other sector start sector protection extended sector plscnt = 25? device failed remove v id from reset completed remove v id from reset write reset command write reset command reset = v id wait to 4 s protection entry? to setup sector protection write xxxh/60h write spa/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) time out 150 s to verify sector protection write spa/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? ? device is operating in temporary sector read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt setup next sector address no yes yes unprotection mode fast mode algorithm
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 47 (8) embedded program tm algorithm for fast mode fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify byte? no program address/program data data polling device last address ? programming completed xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 48 ordering information part number package access time sector config uration remarks mbm29lv002tc-70ptn mbm29lv002tc-90ptn 40-pin plastictsop(1) (fpt-40p-m06) (normal bend) 70 90 top sector mbm29lv002tc-70ptr mbm29lv002tc-90ptr 40-pin plastic tsop (1) (fpt-40p-m07) (reverse bend) 70 90 mbm29lv002bc-70ptn mbm29lv002bc-90ptn 40-pin plastic tsop (1) (fpt-40p-m06) (normal bend) 70 90 bottom sector mbm29lv002bc-70ptr mbm29lv002bc-90ptr 40-pin plastic tsop (1) (fpt-40p-m07) (reverse bend) 70 90 mbm29lv002 t c -70 ptn device number/description mbm29lv002 2mega-bit (256k 8-bit) cmos flash memory 3.0 v-only read, program, and erase package type ptn = 40-pin thin small outline package (tsop) normal bend ptr = 40-pin thin small outline package (tsop) reverse bend speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 49 package dimensions (continued) 40-pin plastic tsop(1) (fpt-40p-m06) note1 : * : resin protrusion. (each side : + 0.15 (.006) max) note2 : pins width and pins thickness include plating thickness. note3 : pins width do not include tie bar cutting remainder. dimensions in mm (inches) .007 ? .003 +.001 ? 0.08 +0.03 0.17 "a" 0.10(.004) (mounting height) 1.10 +0.10 ? 0.05 +.004 ? .002 .043 (stand off) 0.10 0.05(.004 .002) (.394 .008) *10.00 0.20 0.10(.004) m (.009 .002) 0.22 0.05 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. index 21 20 40 1 2003 fujitsu limited f40007s-c-3-4 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part 0.50(.020)
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 50 40-pin plastic tsop(1) (fpt-40p-m07) note1 : * : resin protrusion. (each side : + 0.15 (.006) max) note2 : pins width and pins thickness include plating thickness. note3 : pins width do not include tie bar cutting remainder. dimensions in mm (inches) ? .003 +.001 .007 ? 0.08 +0.03 0.17 "a" 0.10(.004) (mounting height) 1.10 +0.10 ? 0.05 +.004 ? .002 .043 (stand off) 0.10 0.05(.004 .002) 0.10(.004) m (.009 .002) 0.22 0.05 (.394 .008) *10.00 0.20 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. index 21 20 40 1 2003 fujitsu limited f40008s-c-3-4 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part 0.50(.020)
retired product y ds05-20863-5e_july 26, 2007 mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 51 revision history revision ds05-20863-5e july 26, 2007 the following comment is added. this product has been retired and is not reco mmended for new designs. availability of this document is retained for reference and historical purposes only.
mbm29lv002tc -70/-90 /mbm29lv002bc -70/-90 retired product y ds05-20863-5e_july 26, 2007 fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9100 fax: +1-408-432-9044 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0303 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to c onsult with fujitsu sales representatives before ordering. the information, such as descrip tions of function and application circuit examples, in this document are presented solely for the purpose of reference to show exam ples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you devel op equipment incorporating the device based on such inform ation, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any dama ges whatsoever arising out of the use of the information. any information in this documen t, including descriptions of function and schematic diagrams, sh all not be construed as license of the use or exercise of any intellectual propert y right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or ot her right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as c ontemplated for gene ral use, including without limitation, ordinary industrial us e, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extrem ely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or othe r loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight cont rol, air traffic control, mass transpor t control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liab le against you and/or any third party for any claims or da mages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dama ge or loss from such failures by incorporating safety design meas ures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and othe r abnormal operating conditions. if any products described in th is document repr esent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japane se government will be required for export of those products from japan.

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